Shadow Transmit Holding Register (n)
| STHRN | This is a shadow field for the UART_THR[THR] and has been allocated 16 32-bit locations so as to accommodate burst accesses from the master. This register contains data to be transmitted on the UART_TX in UART mode. Data should only be written to the UART_THR when the UART_LSR[THRE] bit is set. If FIFOs are disabled (UART_FCR[FIFOE] set to 0) and UART_LSR[THRE] is set, writing a single character to the UART_THR[THR] clears the UART_LSR[THRE]. Any additional writes to the UART_THR[THR] before the UART_LSR[THRE] is set again causes the UART_THR[THR] data to be overwritten. If FIFOs are enabled (UART_FCR[FIFOE] set to 1) and UART_LSR[THRE] is set, 32 data characters may be written to the UART_THR[THR] before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. |